1. The Field of the Invention
The present invention relates to methods of forming electrical contacts on silicon substrates of in-process integrated circuit wafers. More particularly, the present invention is directed to a method of forming an electrical contact including a diffusion barrier formed by metal ion implantation, the electrical contact being formed on a silicon substrate of an in-process integrated circuit wafer.
2. The Relevant Technology
Recent advances in computer technology and in electronics in general are attributable to a great degree to the progress achieved by the integrated circuit industry in electronic circuit integration and miniaturization. This progress has resulted in increasingly compact and efficient semiconductor devices, attended by an increase in the complexity and number of such devices aggregated on a single integrated circuit wafer. The smaller and more complex devices, including resistors, capacitors, diodes, and transistors, have been achieved, in part, by reducing device sizes and spacing and by reducing the junction depth of active regions formed on the silicon substrate of integrated circuit wafers. The smaller and more complex devices have also been achieved by stacking the devices at various levels on the wafer.
Among the features which are being reduced in size are the electrical contacts through which electrical communication is made between discrete semiconductor devices on the varying levels of the wafer. In order to continue in the process of reducing integrated circuit size, however, new methods of forming electrical contacts which overcome certain problems existing in the art are required.
As an example of the problems currently encountered in forming electrical contacts electrical contacts have historically been formed from aluminum or aluminum alloy metallization. Aluminum, however, presents the problem of spiking. Spiking results in the dissolution of silicon from active regions of the semiconductor devices into the aluminum metallization and the dissolution of aluminum into the active regions.
Electrical contacts have more recently been metallized with tungsten with the formation of what is known as a xe2x80x9ctungsten plug.xe2x80x9d The tungsten plug formation process does not incur spiking, but has proven problematic for other reasons, however, and these problems are heightened by the continuous miniaturization of the integrated circuit and the modern xe2x80x9cstackedxe2x80x9d construction of such circuits.
The tungsten plug is typically deposited by chemical vapor deposition (CVD) in an atmosphere of fluorine, which attacks silicon, creating xe2x80x9cworm holesxe2x80x9d into the active region. Worm holes formed from this reaction can extend completely through the active region, thereby shorting it out and causing the device to fail. As a further problem associated with the tungsten plug structure of the prior art, the tungsten metallization complicates the electrical contact formation process because it does not adhere well directly to silicon or oxide.
In order to eliminate the problems associated with the reaction between the silicon substrate and the metallization material, prior art methods have typically employed a diffusion barrier structure that is provided between the metallization material and the active region. The diffusion barrier prevents the inter diffusion of silicon of the active region and aluminum of the metallization material. It also provides a surface to which the tungsten will adhere and prevents fluorine from diffusing into the active region.
Prior art FIGS. 1 through 4 of the accompanying drawings depict one conventional method known in the art of forming contact structures having a diffusion barrier. As shown in FIG. 1, a contact opening 16 is first etched through an insulating layer 14 overlying an active region 12 on a silicon substrate 10. Active region 12 typically comprises a doped silicon region such as a source or a drain of a MOS transistor. Insulating layer 14 typically comprises a passivation layer of intentionally formed silicon dioxide or borophosphosilicate glass (BPSG). Contact opening 16 provides a route for electrical communication for active region 12 through the surface of insulating layer 14. As shown in FIG. 2, a titanium layer 20 is sputtered over contact opening 16 in a further step, and coats the exposed surface of active region 12.
A high temperature anneal step is then conducted in an atmosphere of predominantly nitrogen gas (N2). Titanium layer 20 reacts with the silicon of active region 12 during the anneal and is transformed into a dual layer. In forming the new dual layer, the lower portion of titanium layer 20 overlying active region 12 reacts with a portion of the silicon in active region 12 to form a titanium silicide (TiSix) region 22. Concurrently, the upper portion of titanium layer 20 reacts with the nitrogen gas to form a titanium nitride (TiNx) layer 24. The resulting structure is shown in FIG. 3. Titanium silicide layer 22 provides a conductive interface at the surface of active region 12. Titanium nitride layer 24 formed above titanium silicide layer 22 acts as a diffusion barrier to the interdiffusion of tungsten and silicon, or to the interdiffusion of aluminum and silicon, as mentioned above.
Titanium nitride layer 24 can also be formed with chemical vapor deposition. A typical chemical vapor deposition process comprises the use of a precursor such as a metal organic or a halide, which is thermally decomposed, reacted with a gas such as NH3, or plasma-assist deposited.
The next step, shown in FIG. 4, is the deposition of the metallization layer. In tungsten plug formation, metallization is achieved by the chemical vapor deposition of tungsten to form metallization layer 25. Titanium nitride layer 24 helps improve the adhesion between the walls of the opening and the tungsten metallization material. It also acts as a barrier against the diffusion of metallization layer 25 into the active region 12, and vice-versa.
Another function of depositing titanium layer 20 in contact opening 16 is to remove native silicon dioxide (SiO2) which forms whenever the in-process integrated circuit wafer is exposed to oxygen, such as by way exposure to ambient air. Typical native silicon dioxide layers have a thickness of about 20 Angstroms. Such a native silicon dioxide layer 15 is shown in FIG. 1. Native silicon dioxide layer 15 is highly insulative and can cause a high contact resistance so as to result in failure of the device being formed. Titanium layer 20 of FIG. 2 reacts with and breaks down silicon dioxide layer 15. In the process, a portion of titanium layer 20 is consumed. As a result, titanium layer 20 must be deposited in contact opening 16 in sufficient thickness to react with native oxide layer 15 and to also form an effective diffusion barrier.
One problem involved with the titanium silicide diffusion barrier structure is the poor step coverage provided by current titanium deposition methods. FIG. 5 depicts the results of a typical attempt to deposit titanium with a sufficient thickness in a high aspect ratio contact opening. Note the cusping 26 or xe2x80x9cbread loafingxe2x80x9d of titanium on the surface of contact opening 16. A result of cusping 26 is that contact opening 16 is eventually closed off, and cannot be completely filled. Thus, a void area, known as a xe2x80x9ckeyhole,xe2x80x9d 28 is formed. Keyhole 28 increases the contact resistance of the electrical contact being formed, resulting in slower device performance. This is ultimately a failure condition of the integrated circuit. Also, keyhole 28 can open up during later processing steps and allow caustic materials inside, which will erode contact opening 16. This is also a failure condition.
A further problem of prior art methods involves the migration of the integrated circuit industry toward high aspect ratios. As device dimensions continue to shrink and the contact openings become deeper and narrower, contact walls become vertical, and current metal deposition techniques fail to provide the necessary step coverage to create adequate contact with underlying active regions. Accordingly, it becomes increasingly difficult to produce a uniform titanium layer at the bottom of the contact opening of sufficient thickness for forming the titanium silicide diffusion barrier.
FIG. 1 shows the dimensions used to calculate the aspect ratio, which is the ratio of the height H to the width W. In order to introduce a sufficiently thick layer of titanium to create an effective diffusion barrier, the aspect ratio of contact openings in the prior art are typically kept relatively low, generally under 2 to 1. This aspect ratio limitation presents a hinderance to current miniaturization efforts.
A further problem associated with high aspect ratios in tungsten plug and titanium nitride layer formation is the formation of a uniform layer of titanium at the bottom of contact opening 16 seen in FIG. 1. The sputtered titanium has a generally angular trajectory that coats the sidewalls and surface of contact opening 16, but is incapable of forming a uniform layer of titanium 20 in the bottom of contact opening 16, particularly in the far corners 17 of contact opening 16. Without this uniform layer, it is very difficult to sufficiently form the diffusion barrier of titanium silicide. The result is high contact resistance and even device failure when aspect ratios are increased beyond about 2 to 1.
The contact opening aspect ratio is expected to continue increase over the next several generations of processes. Aspect ratios of 10 to 1 could become common. In the absence of a solution, the formation of a low resistive contact will become increasingly problematic.
In order to increase the amount of titanium at the bottom of the contact opening, collimated sputtering is currently used for depositing titanium in high aspect ratio contacts. This technology has several limitations, however, in the form of a very low throughput, poor cleanliness, and the necessity of frequent collimator changes. Also, only a fraction of the metal deposited on the top of the contact opening actually reaches the bottom with collimator sputtering. In current processes, the sputtered titanium still does not fully coat the corners of the contact, requiring additional materials such as titanium nitride to be deposited over the top of the titanium. In addition, a tungsten deposition having a thickness of several thousand Angstroms, which is necessary to achieve sufficient coverage on the bottom of contact opening 16, still continues to cause cusping 26 at the top of contact opening 16 so as to reduce the contact opening size and make subsequent CVD depositions of tungsten or other metallization materials more difficult. Collimated sputtering is predicted to be less effective for future high aspect ratio processes because of these limitations, and will ultimately become unusable.
Thus, it is apparent that an electrical contact and a corresponding method for forming the electrical contact are needed which overcome the problems existing in the prior art. Specifically, an electrical contact is needed which can form a sufficient diffusion barrier, and which adheres well to oxide sidewalls. A method of forming the electrical contact is also needed which can be used with high aspect ratio contact openings, which can provide uniform step coverage over the contact openings, and which will sufficiently deposit titanium into remote corners of the contact openings for forming a uniform metal silicide diffusion barrier over underlying active regions.
The present invention seeks to resolve the above and other problems which have been experienced in the art. More particularly, the present invention constitutes an advancement in the art by providing a method for forming an electrical contact on an inprocess integrated circuit wafer which achieves each of the objects listed below.
It is an object of the present invention to provide a method for forming an electrical contact capable of utilizing a high aspect ratio of greater than about 4 to 1.
It is also an object of the present invention to provide such a method which results in a uniform metal silicide layer in the bottom of the contact opening, including in remote corners.
It is another object of the present invention to provide such a method which results in an electrical contact which adheres well to oxide.
It is likewise an object of the present invention to provide such a method which results in an electrical contact which provides a suitable diffusion barrier.
It is another object of the present invention to provide such a method which results in an electrical contact which provides a low contact resistance.
It is a further object of the present invention to provide such a method which is cleaner than the collimated sputtering methods of the prior art.
To achieve the foregoing objects, and in accordance with the invention as embodied and broadly described herein in the preferred embodiment, a method for forming an electrical contact on an in-process integrated circuit wafer is provided. The electrical contact formed thereby is well suited for the use of a tungsten plug. Many of the limitations of the prior art are overcome by the novel method of the present invention for forming the electrical contact.
The resulting electrical contact comprises an underlying layer of titanium silicide, an intermediate layer of titanium nitride, and an upper layer of tungsten. The resulting electrical contact adheres well to oxide sidewalls. Also, step coverage is improved, as the problems of cusping and keyhole formation are overcome by the use of implantation to form the titanium silicide. In addition, an effective diffusion barrier as well as low contact resistance are provided by the electrical contact.
The first step of the method of the present invention in one embodiment comprises providing a silicon substrate on an in-process integrated circuit wafer. Next, a film is formed on the silicon substrate and typically comprises an insulating layer such as borophosphosilicate glass (BPSG). Underneath the insulating layer is typically formed an active region for electrical communication with a transistor gate or capacitor plate. The insulating layer is then patterned with photoresist and etched to form the contact opening.
The next step of the present invention comprises implanting metal ions into the bottom of the contact opening. The metal ions preferably comprise titanium and are deposited with a concentration of preferably about 3.3xc3x971016 to about 6.6xc3x971017 atoms per square centimeter of silicon. Implantation allows nearly 100% of the sputtered material to reach the bottom of the contact opening, including in the corners. Next, the in-process integrated circuit wafer is annealed in order to react the sputtered titanium with the silicon in the active region to form a titanium silicide layer of a thickness preferably of about 300 Angstroms. Also, the active region is returned to its prior crystalline state by the anneal. In a further step, a layer of titanium nitride is formed over the surface of the contact opening. The titanium nitride is preferably deposited by first sputter depositing a layer of titanium into the contact opening and then performing a second anneal of the in-process integrated circuit wafer. The second anneal is conducted in an atmosphere of nitrogen to form a titanium nitride layer. Finally, the remainder of the contact opening is metallized, preferably by CVD deposition of tungsten into the remainder of the contact opening.
In an alternative embodiment, the contact opening can be used to form a self-aligned contact. When forming a self-aligned contact, the step of forming a contact opening further comprises forming a dual gate structure over an active region on the silicon substrate, with an aperture formed in the center of the dual gate structure over the active region. Next, a layer of silicon nitride is deposited over the dual gate structure. The silicon nitride layer fully covers the gate structure, including a side covering of silicon nitride which is formed at the edges of the aperture. Next, an insulating layer such as BPSG is formed over the silicon nitride layer and the aperture. The insulating layer is planarized, and the contact opening is etched through the insulating layer, exposing the aperture and extending down to an underlying active region.
When using the present invention with a self-aligned contact, a very narrow aperture can be utilized, as the implantation of titanium effectively reaches the far corners of the aperture and forms an effective silicide region at the bottom thereof.
Thus, it can be seen from the above discussion that a method is provided with which an electrical contact is formed that has high adhesion to the sidewalls of the insulating layer. Furthermore, a suitable metal silicide diffusion barrier is formed that has a low resistive interface. Additionally, the electrical contact can be formed to have a high aspect ratio and when so doing, an evenly distributed metal silicide layer can be formed at the bottom thereof.